Senior vhdl design engineer

Werkgever:
Trinamics
Regio:
overijssel
 
Functieomschrijving

Introductie

Our facility is part of amultinational corporation specializing in electronics manufacturing andservices for OEMs. We collaborate with partners in healthcare,semiconductor, automotive, aerospace, and consumer electronics. Our work spans the entire process, from initial design tovolume production and direct delivery to end-users.

Functieomschrijving

As a Senior VHDL Design Engineer with Benchmark, you'll grow in Electrical Engineering. In a global team, you contribute to building complete (sub-)systems, taking charge of designing, implementing, and verifying these systems.

  • You oversee the design, simulation, implementation, and verification of FPGA circuits, employing VHDL code. Your collaboration extends to other disciplines, including hardware and embedded software development.
  • Wat verwachten we van jou?

  • Completed Bachelor or Master in Electrical & Electronics Engineering.
  • Minimum of 8 years of experience in VHDL design within productdevelopment (Intel, Xilinx, Lattice)
  • You bring experience in utilizing simulation tools and measurement equipment for digital circuits, including FPGAs, CPLDs, and standard interfaces like SPI and I2C.
  • Fluent in English
  • Wat kun jij van ons verwachten?

    In addition to a competitive salary (75k-85k), we provide outstanding benefits such as:

  • 27 vacation days and 13 ATV days.
  • Holiday allowance
  • Flexible working hours, allowing you to arrange your schedule, ensuring completion of your work.
  • Quarterly bonus based on revenue (up to 5%)
     Kernwoorden